The invention relates to technologies and techniques for integrated circuit (“IC”) design.
A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. The design of an integrated circuit transforms a circuit description into a geometric description called a layout. The process of converting specifications of an integrated circuit into a layout is called the physical design. After the layout is complete, it is then checked to ensure that it meets the design requirements. The result is a set of design files, which are then converted into pattern generator files. The pattern generator files are used to produce patterns called masks by an optical or electron beam pattern generator. Subsequently, during fabrication of the IC, these masks are used to pattern chips on the silicon wafer using a sequence of photolithographic steps. Electronic components of the IC are therefore formed on the wafer in accordance with the patterns.
Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high level hardware design language. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
An integrated circuit designer may use a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes.
After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then tests and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Common testing and optimization steps include extraction, verification, and compaction. The steps of extraction and verification are performed to ensure that the integrated circuit layout will perform as desired. Extraction is the process of analyzing the geometric layout and material composition of an integrated circuit layout in order to “extract” the electrical characteristics of the designed integrated circuit layout. The step of verification uses the extracted electrical characteristics to analyze the circuit design using circuit analysis tools. Compaction is an example of a tool used to modify a layout in order to make it more suitable for manufacturing.
Designers often use a set of tools to design a chip from its RTL description to its layout implementation. Among these tools, one of the goals of the physical implementation tools is to optimize a chip up to its targeted functional frequency as specified by the designer while taking into account the physical data available from tools such as the placement and route tools. As electronic designs become larger, speeding up the physical implementation process runtime becomes a more important task.
Optimizing a design consists of modifying the database of the chip to meet the timing constraint specified by designers. The optimization engine identifies the most relevant timing paths to optimize and iterates over the instances along these timing paths. For each instance, it applies different actions to improve the slack on the critical path. Most usual known optimization actions are resizing, restructuring, buffering, and moving instances. These actions are normally computation intensive because the timing accuracy which relates to the timing graph, the RC extraction, routing estimation, etc. is usually required or mandatory.
Integrated circuit (IC) packaging or assembly is the final stage of semiconductor device fabrication in which the integrated circuit as manufactured on a piece of semiconductor material such as a wafer will be mounted and interconnected to various other components in or on a chip carrier which provides metal leads or pins protruding from the side(s) of the carrier to interface with other components on a, for example, printed circuit board. In the realm of IC packaging, the I/O placement in digital IC designs may have significant impact on routability and thus the cost of the final packaged IC. Moreover, the I/O placement may also have to conform to various constraints, requirements, conditions, or design rules (collectively design rules). As a result, it may be desirable or required to optimize the placement of I/O pads in both the context of the IC and the package to some degree.
Some modern electronic design automation (EDA) tools for physical implementation (collectively IC design tool) and package layout tools (collectively packaging tool) support some degree of data or model exchange between the packaging and IC design tool. Nonetheless, such an exchange of data or models often occurs through a database such as an Open Access (OA) database and some IC design tool I/O files. This exchange of data or models in known to be slow and often requires explicit actions by the users or designers. As a result, this exchange of data or models is often done in a batch-type optimization of I/O pad placement. What may further exacerbate the issue is that the optimization of I/O pad placement usually requires several time-consuming iterations between the IC design tool and the packaging tool. Usually, a circuit design may be required to work back and forth multiple times between the IC design tool and the packaging tool without knowing what impact there may be on one tool when the circuit designer initiates a change in or a move of a component in the other tool until the circuit designer uses the other tool to analyze the electronic circuit design.
Therefore, there exists a need for a method, system, and computer program product for implementing interactive cross-domain package driven I/O (input/output) planning and placement optimization.